1. Field of the Invention
The present invention relates to voltage comparators with hysteresis, particularly those suitable for implementation in an integrated circuit.
2. Description of Related Art
Comparators are widely used in a variety of electronic equipment to compare the voltages of two analog inputs, and to provide a digital output. This output is driven high or low by the comparator depending upon which of the inputs is at the higher voltage. Adding hysteresis can be useful in many applications to provide noise immunity and to prevent the output from "chattering" when the inputs hover near the threshold of the comparator.
FIG. 1 shows a representation of a comparator 10 comprising two input leads 11 and 12 and an output lead 13. The differential input voltage V.sub.IN is coupled to leads 11 and 12, and output lead 13, which is referenced to comparator reference 14, will be driven high if the voltage coupled to lead 11 is greater than the voltage coupled to lead 12. Conversely, the output lead 13 will be driven low if the voltage coupled to lead 11 is less than the voltage coupled to lead 12.
FIG. 2 illustrates the well-known hysteresis characteristic showing a positive decision voltage V.sub.P and a negative decision voltage V.sub.N. In operation, a comparator exhibiting this hysteresis characteristic will require the differential input voltage V.sub.IN to exceed the decision voltage V.sub.P before the output of the comparator will be driven high. Subsequently, once output 13 is high, the V.sub.IN must drop to a value less than the decision voltage V.sub.N to cause the output to switch low. Circuit advantages can result if the decision voltages V.sub.P and V.sub.N are tightly controlled.
Traditionally, hysteresis in a comparator has been implemented by utilizing a gain stage in the forward path and a hysteresis control block in the feedback path. FIG. 3 shows a hysteresis comparator 10 comprising non-inverting input lead 11, inverting input lead 12 coupled to comparator reference 14, gain stage 21, output lead 13 for providing an output voltage, and hysteresis control block 30. In operation, hysteresis control block 30 responds to the output node 32 of gain stage 21 and provides a voltage level on feedback node 34 which gives rise to the hysteresis characteristic of FIG. 2.
Transistors 21 and 22 and resistors 31 and 33 form a resistive divider which sets the approximate voltage of feedback node 34. Two inverters, comprising transistors 25 and 26 and transistors 23 and 24, drive node 36 high or low corresponding to the output 32 of gain stage 21. Depending on the logic state of node 36, the current through resistor 35 will then pull the voltage of node 34 towards one of the reference voltages V.sub.REFP or V.sub.REFN, coupled to nodes 38 and 39, respectively. If the voltage on node 32 is high, hysteresis control block 30 will produce a higher voltage level on feedback node 34. Similarly, if the voltage on node 32 is low, the hysteresis control block 30 will produce a lower voltage level on feedback node 34. The design equations for this circuit can be written as: ##EQU1## are the onresistances of transistors 21, 22, 23, and 24 respectively, and where R.sub.31, R.sub.33 and R.sub.35 are the resistances of respective resistors 31, 33 and 35.
Transistors 21 and 22, which are always on, are included in this circuit to allow better control of K.sub.1 R.sub.1 /R.sub.1 and K.sub.2 R.sub.2 /R.sub.2 ratios, and therefore better control of K.sub.1 and K.sub.2 values.
There are several disadvantages to the circuit of FIG. 3, especially when trying to control the variations of V.sub.P and V.sub.N. First, controlling the R.sub.1 /R.sub.2 value in equations 1 and 2 requires balancing the on-resistance, or 1/g.sub.ds, of an n-channel transistor to that of a p-channel transistor. Because of different processing steps used to fabricate the n-channel and p-channel transistors, this balancing cannot be done by just choosing an appropriate transistor width ratio. The remaining variations in R.sub.1 /R.sub.2 ratio can be minimized by choosing both large resistors and large transistors (i.e., small 1/g.sub.ds), but both of these choices require a large silicon area to implement.
Secondly, the more profound disadvantage of the circuit of FIG. 3 is the requirement of two critical reference voltages V.sub.REFP and V.sub.REFN.The regulation of these voltages with respect to the comparator reference voltage 14 directly impacts the stability of decision voltages V.sub.P and V.sub.N.
Another of form of hysteresis comparator is shown in FIG. 4. A resistor divider comprised of resistors 40 and 42 generates a voltage on node 46 which is either higher or lower than the input voltage coupled directly to lead 11, depending upon whether the comparator output 13 is high or low. To understand the operation of this circuit, assume that the voltage on lead 11 is well below the voltage of lead 12 (by an amount exceeding the magnitude of V.sub.N). Gain stage 21 will drive node 13 low, which causes node 48 to also be driven low by the two inverters comprised of transistors 43 and 47 and transistors 41 and 45. Due to the resistive divider, node 46 will be even lower than node 11. Subsequently, when node 11 rises to a voltage high enough to cause the voltage on node 46 to increase above the voltage of node 12, the gain stage will switch to a high state and subsequently cause node 48 to be driven high. This causes the voltage on node 46 to now be much higher than the voltage on lead 11, further reinforcing the high output state of gain stage 21. The design equations for this circuit can be written as: ##EQU2##
In the above equations the quantities 1/g.sub.ds(41) and 1/g.sub.ds(45) represent the on-resistances of transistors 41 and 45, respectively.
This circuit suffers from at least two disadvantages. Controlling the resistance ratios in equations 3 and 4 above involve relying on process-dependent resistances of n-channel and p-channel transistors. As before, this effect can be minimized by choosing large resistors and transistors, but this consumes substantial silicon area.
Another disadvantage of this circuit is the requirement for reference voltages V.sub.REFP and V.sub.REFN, and the regulation necessary on these critical references with respect to the comparator reference 14 which is coupled to lead 12.